View CY7C43683AV_319271.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

V
CY7C43643AV PRELIMINARY CY7C43663AV/CY7C43683AV
3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO w/ Bus Matching
Features
* High-speed, low-power, unidirectional, First-In FirstOut (FIFO) memories w/ bus matching capabilities * 1Kx36 (CY7C43643AV) * 4Kx36 (CY7C43663AV) * 16Kx36 (CY7C43683AV) * 0.25-micron CMOS for optimum speed/power * High-speed 133-MHz operation (7.5-ns read/write cycle times) * Low power -- ICC= 60 mA -- ISB= 12 mA * Fully asynchronous and simultaneous read and write operation permitted * Mailbox bypass register for each FIFO * Parallel and Serial Programmable Almost Full and Almost Empty flags * Retransmit function * Standard or FWFT mode user selectable * Partial Reset * Big or Little Endian format for word or byte bus sizes * 128-Pin TQFP packaging * 3.3V pin-compatible, feature enhanced, density upgrade to IDT723623/33/43 family * Easily expandable in width and depth
Logic Block Diagram
MBF1 CLKA CSA W/RA ENA MBA RT
Input Register
Output Register
1K/4K/16K x36 Dual Ported Memory
Bus Matching
Port A Control Logic
Mail1 Register
CLKB CSB W/RB ENB MBB BE BM SIZE
Port B Control Logic
MRS1 MRS2 PRS
FIFO, Mail1 Mail2 Reset Logic
Write Pointer
Read Pointer
FF/IR AF
Status Flag Logic 36 Programmable Flag Offset Registers Timing Mode
EF/OR AE
SPM FS0/SD FS1/SEN A0-35
B0-35 BE/FWFT
36
Mail2 Register
MBF2
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 August 30, 1999
PRELIMINARY
Pin Configuration
TQFP Top View
CY7C43643AV CY7C43663AV/CY7C43683AV
VCC AF NC MBF2 MBA MRS1 FS0/SD GND GND FS1/SEN MRS2 MBB
W/RA ENA CLKA GND A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 FWFT/STAN GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 GND A11 A10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
CSA FF/IR NC PRS
NC EF/OR NC GND CSB W/RB ENB
MBF1 VCC AE
CLKB VCC VCC B35 B34 B33 B32 GND GND B31 B30 B29 B28 B27 B26 RT B25 B24 BM GND B23 B22 B21 B20 B19 B18 GND B17 B16 SIZE VCC B15 B14 B13 B12 GND B11 B10
CY7C43643AV CY7C43663AV CY7C43683AV
GND A5 A4 A3 SPM VCC A2 A1 A0 GND B0 B1
2
GND B6 VCC B7 B8 B9
A9 A8 A7 A6
B2 B3 B4 B5
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
PRELIMINARY
Functional Description
The CY7C436X3AV is a monolithic, high-speed, low-power, CMOS Unidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 133 MHz and has read access times as fast as 6 ns. FIFO data on Port B can be output in 36-bit, 18-bit, or 9-bit formats with a choice of Big or Little Endian configurations. The CY7C436X3AV is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple unidirectional interface between microprocessors and/ or buses with synchronous control. Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox registers' width matches the selected Port B bus width. Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. Two kinds of reset are available on the CY7C436X3AV: Master Reset and Partial Reset. Master Reset initializes the read and write pointers to the first location of the memory array, configures the FIFO for Big or Little Endian byte arrangement, and selects serial flag programming, parallel flag programming, or one of the three possible default flag offset settings, 8, 16, or 64. The FIFO also has two Master Reset pins, MRS1 and MRS2. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programming method and partial flag default offsets) are retained. Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings. The FIFO has its own independent Partial Reset pin, PRS. The CY7C436X3AV have two modes of operation: In the CY Standard Mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in mem-
CY7C43643AV CY7C43663AV/CY7C43683AV
ory). In the First-Word Fall-Through Mode (FWFT), the first long-word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the FWFT/STAN pin during FIFO operation determines the mode in use. The FIFO has a combined Empty/Output Ready flag (EF/OR) and a combined Full/Input Ready flag (FF/IR). The EF and FF functions are selected in the CY Standard Mode. EF indicates whether the memory is full or not. The IR and OR functions are selected in the First-Word Fall-Through Mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. The FIFO has a programmable Almost Empty flag (AE) and a programmable Almost Full flag (AF). AE indicates when a selected number of words written to FIFO memory achieve a predetermined "almost empty state." AF indicates when a selected number of words written to the memory achieve a predetermined "almost full state." IR and AF are synchronized to the port clock that writes data into its array. OR and AE are synchronized to the port clock that reads data from its array. Programmable offset for AE and AF are loaded in parallel using Port A or in serial via the SD input. Three default offset settings are also provided. The AE threshold can be set at 8, 16, or 64 locations from the empty boundary and AF threshold can be set at 8, 16, or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset. Two or more devices may be used in parallel to create wider data paths. If at any time the FIFO is not actively performing a function, the chip will automatically power down. During the Power Down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the Power Down state. The CY7C436X3AV are characterized for operation from 0C to 70C. Input ESD protection is greater than 2001V, and latchup is prevented by the use of guard rings.
Selection Guide
CY7C43643/63/83AV -7 Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Active Power Supply Current (ICC1 ) (mA) Commercial Industrial CY7C43643AV Density Package 1K x 36 128 TQFP CY7C43663AV 4K x 36 128 TQFP 133 6 7.5 3 0 6 60 CY7C43643/63/83AV -10 100 8 10 4 0 8 60 CY7C43643/63/83AV -15 66.7 10 15 5 0 10 60 60 CY7C43683AV 16K x 36 128 TQFP
3
PRELIMINARY
Pin Definitions
Signal Name A0-35 AE Description Port A Data Almost Empty Flag (Port B) Almost Full Flag I/O I O
CY7C43643AV CY7C43663AV/CY7C43683AV
Function 36-bit unidirectional data port for side A. Programmable Almost Empty flag synchronized to CLKA. It is LOW when the number of words in the FIFO2 is less than or equal to the value in the Almost Empty A offset register, X. Programmable Almost Full flag synchronized to CLKA. It is LOW when the number of empty locations in the FIFO is less than or equal to the value in the Almost Full A offset register, Y. 36-bit unidirectional data port for side B. This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this case, depending on the bus size, the most significant byte or word on Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Little Endian operation. In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects CY Standard Mode, a LOW selects First-Word Fall-Through Mode. Once the timing mode has been selected, the level on FWFT must be static throughout device operation. A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to select the bus size and endian arrangement for Port B. The level of BM must be static throughout device operation. CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to the LOWto-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or coincident to CLKA. FB/IR, EF/OR, AF, and AE are all synchronized to the LOW-to-HIGH transition of CLKB. CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on Port A. The A0-35 outputs are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on Port B. The B0-35 outputs are in the high-impedance state when CSB is HIGH. This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function is selected. OR indicates the presence of valid data on B0-35 outputs, available for reading. FF/OR is synchronized to the LOW-to-HIGH transition of CLKB. ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A. ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. This is a dual-function pin. In the CY Standard Mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA. FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset register programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load from Port A, and serial load. When serial load is selected for flag offset register programming, FS1/ SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 20 for the CY7C43643, 24 for the CY7C43663, and 28 for the CY7C43683. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB.
AF
O
B0-35 BE/FWFT
Port B Data Big Endian/ First-Word FallThrough Select
O I
BM
Bus Match Select (Port B)
I
CLKA
Port A Clock
I
CLKB
Port B Clock
I
CSA CSB EF/OR
Port A Chip Select Port B Chip Select Empty/Output Ready Flag (Port B) Port A Enable Port B Enable Port B Full/Input Ready Flag
I I O
ENA ENB FF/IR
I I O
FS1/SEN
Flag Offset Select 1/Serial Enable Flag Offset Select 0/Serial Data
I
FS0/SD
I
4
PRELIMINARY
Pin Definitions (continued)
Signal Name MBA MBB Description Port A Mailbox Select Port B Mailbox Select Mail1 Register Flag I/O I I
CY7C43643AV CY7C43663AV/CY7C43683AV
Function A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-35 outputs are active, a HIGH level on MBB selects data from the Mail1 register for output and a LOW level selects FIFO output register data for output. MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1 register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset. MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2 register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset. A LOW on this pin initializes the FIFO read and write pointers to the first location of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects the programming method (serial or parallel) and one of three programmable flag default offsets. It also configures Port B for bus size and endian arrangement. Four LOW-toHIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1 is LOW. A LOW on this pin initializes the Mail2 Register. A LOW on this pin initializes the FIFO read and write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. A LOW strobe on this pin will retransmit data on FIFO from the location of the write pointer at the last Partial or Master reset. A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation. A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel programming or default offsets (8, 16, or 64). A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of CLKA. The A0-35 outputs are in the high-impedance state when W/RA is HIGH. A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of CLKB. The B0-35 outputs are in the high-impedance state when W/RB is LOW.
MBF1
O
MBF2
Mail2 Register Flag
O
MRS1
Master Reset
I
MRS2 PRS
Master Reset Partial Reset
I I
RT SIZE
Retransmit Bus Size Select
I I
SPM W/RA
Serial Programming Port A Write/ Read Select Port B Write/ Read Select
I I
W/RB
I
5
PRELIMINARY
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................-65C to +150C Ambient Temperature with Power Applied ...............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ......................................-0.5V to VCC+0.5V DC Input Voltage[2]...................................-0.5V to VCC+0.5V
CY7C43643AV CY7C43663AV/CY7C43683AV
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC[3] 3.3V 10% 3.3V 10%
Electrical Characteristics Over the Operating Range
CY7C43643/63/83AV Parameter VOH VOL VIH VIL IIX IOZL IOZH ICC1[4] ISB[5] Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output OFF, High Z Current Active Power Supply Current Average Standby Current VCC = Max. VSS < VO< V CC Com'l Ind Com'l Ind Test Conditions VCC = 3.0V, IOH = -2.0 mA VCC = 3.0V, IOL = 8.0 mA 2.0 -0.5 -10 -10 Min. 2.4 0.5 VCC 0.8 +10 +10 60 60 12 12 Max. Unit V V V V A A mA mA mA mA
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 4 8 Unit pF pF
Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. 3. Operating VCC Range for -7 speed is 3.3V 5%. 4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded. 5. All inputs = VCC - 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded. 6. Tested initially and after any design or process changes that may affect these parameters.
6
PRELIMINARY
AC Test Loads and Waveforms (-10, -15)
R1=330 3.3V OUTPUT CL=30 pF INCLUDING JIG AND SCOPE R2=680 3.0V GND 3 ns
CY7C43643AV CY7C43663AV/CY7C43683AV
ALL INPUT PULSES
90% 10% 90% 10% 3 ns
AC Test Loads and Waveforms (-7)
VCC/2 50 I/O
Z0=50 3.0V GND 3 ns
ALL INPUT PULSES
90% 10% 90% 10% 3 ns
Switching Characteristics Over the Operating Range
CY7C43643/63/ 83AV -7 Parameter fS tCLK tCLKH tCLKL tDS tENS tRSTS tFSS tBES tSPMS tSDS tSENS tFWS tDH tENH Description Clock Frequency, CLKA or CLKB Clock Cycle Time, CLKA or CLKB Pulse Duration, CLKA or CLKB HIGH Pulse Duration, CLKA or CLKB LOW Set-Up Time, A0-35 before CLKA and B0-35 before CLKB Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA; CSB, W/RB, ENB, and MBB before CLKB Set-Up Time, MRS1/MRS2 or PRS LOW before CLKA or CLKB[7] Set-Up Time, FS0 and FS1 before MRS1/MRS2 HIGH Set-Up Time, BE/FWFT before MRS1/MRS2 HIGH Set-Up Time, SPM before MRS1/MRS2 HIGH Set-Up Time, FS0/SD before CLKA Set-Up Time, FS1/SEN before CLKA Set-Up Time, FWFT before CLKA Hold Time, A 0-35 after CLKA and B 0-35 after CLKB Hold Time, CSA, W/RA, ENA, and MBA after CLKA; CSB, W/RB, ENB, and MBB after CLKB 7.5 3.5 3.5 3 3 2.5 5 5 5 3 3 0 0 1 Min. Max. 133 10 4 4 4 4 4 7 7 7 4 4 0 0 2 CY7C43643/ 63/83AV -10 Min. Max. 100 15 6 6 5 5 5 7.5 7.5 7.5 5 5 0 0 0 CY7C43643/ 63/83AV -15 Min. Max. 67 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 7. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
7
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)
CY7C43643AV CY7C43663AV/CY7C43683AV
CY7C43643/63/ 83AV -7 Parameter tRSTH tFSH tBEH tSPMH tSDH tSENH tSPH tSKEW1
[8]
CY7C43643/ 63/83AV -10 Min. 1 1 0 0 1 5 2 7.5 8 Max.
CY7C43643/ 63/83AV -15 Min. 4 2 2 2 0 0 2 7.5 12 Max. Unit ns ns ns ns ns ns ns ns ns 10 10 10 10 10 10 ns ns ns ns ns ns
Description Hold Time, MRS1/MRS2 or PRS LOW after CLKA or CLKB[7] Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH Hold Time, BE/FWFT after MRS1/MRS2 HIGH Hold Time, SPM after MRS1/MRS2 HIGH Hold Time, FS0/SD after CLKA Hold Time, FS1/SEN after CLKA Hold Time, FS1/SEN HIGH after MRS1/MRS2 HIGH Skew Time between CLKA and CLKB for EF/OR and FF/IR Skew Time between CLKA and CLKB for AE and AF Access Time, CLKA to A0-35 and CLKB to B0-35 Propagation Delay Time, CLKA to FF/IR Propagation Delay Time, CLKB to EF/OR Propagation Delay Time, CLKB to AE Propagation Delay Time, CLKA to AF Propagation Delay Time, CLKA to MBF1 LOW or MBF2 HIGH and CLKB to MBF2 LOW or MBF1 HIGH Propagation Delay Time, CLKA to B0-35[9] and CLKB to A0-35[10] Propagation Delay Time, MBA to A0-35 Valid and MBB to B0-35 Valid Propagation Delay Time, MRS1/MRS2 or PRS LOW to AE LOW, AF HIGH,FF/ IR LOW, EF/ OR LOW and MBF1/MBF2 HIGH Enable Time, CSA or W/RA LOW to A0-35 Active and CSB LOW and W/RB HIGH to B 0-35 Active Disable Time, CSA or W/RA HIGH to A0-35 at High Impedance and CSB HIGH or W/RB LOW to B0-35 at High Impedance Retransmit Pulse Width Retransmit Recovery Time
Min. 1 1 0 0 0 5 2 7.5 7 1 1 1 1 1 0
Max.
tSKEW2[8] tA tWFF tREF tPAE tPAF tPMF
6 6 6 6 6 6
1 1 1 1 1 0
8 8 8 8 8 8
3 2 1 1 1 0
tPMR tMDV tRSF
1 1 1
7 6 6
2 2 1
11 9 10
3 3 1
12 11 15
ns ns ns
tEN tDIS
1 1
5 5
2 1
8 6
2 1
10 8
ns ns
tPRT tRTR
60 90
60 90
60 90
ns ns
Notes: 8. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB cycle. 9. Writing data to the Mail1 register when the B0-35 outputs are active and MBB is HIGH. 10. Writing data to the Mail2 register when the A0-35 outputs are active and MBA is HIGH.
8
PRELIMINARY
Switching Waveforms
Master Reset Loading X and Y with a Preset Value of Eight CLKA CLKB MRS1, MRS2 BE/FWFT
tSPMS t RSTS
CY7C43643AV CY7C43663AV/CY7C43683AV
[11]
tRSTS t FWS
tBES
tBEH
tSPMH
SPM
tFSS tFSH
FS1/SEN, FS0/SD FF/IR
tRSF
tWFF
tRSF
EF/OR
tRSF
AE
tRSF
AF
tRSF
MBF1
Note: 11. PRS1 must be HIGH during Master Reset.
9
PRELIMINARY
Switching Waveforms (continued)
Partial Reset (CY Standard and FWFT Modes) CLKA CLKB
tRSTS
CY7C43643AV CY7C43663AV/CY7C43683AV
[12]
tRSTH
PRS
tRSF tWFF
FF/IR
tRSF
EF/OR
tRSF
AE
tRSF
AF
tRSF
MBF1
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (CY Standard and FWFT Modes) [13] CLKA MRS1, MRS2 SPM
tFSS t FSH
tFSS
tFSH
FS1/SEN, FS0/SD FF/IR
tWFF tENS tENH tSKEW1[14]
ENA
tDS tDH
A0-35
AF Offset (Y) AE Offset (X) First Word to FIFO
Notes: 12. MRS1/MRS2 must be HIGH during Partial Reset. 13. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles. 14. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IR to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising edge of CLKB is less than tSKEW1, then FF/IR may transition HIGH one cycle later than shown.
10
PRELIMINARY
Switching Waveforms (continued)
Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (CY Standard and FWFT Modes) CLKA MRS1, MRS2
tFSS tFSH
CY7C43643AV CY7C43663AV/CY7C43683AV
[15]
SPM
tWFF
FF/IR
tFSS tSPH tSENS tSENH tSENS tSENH
FS1/SEN
tSDS tSDH tSDS tSDH
FS0/SD [16]
AF Offset (Y) MSB AE Offset (X) LSB
Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)
tCLK tCLKH tCLKL
CLKB EF/OR CSB W/RB MBB
tENS tENH tENS tENH t ENS tEN
ENB B0-35 (Standard Mode)
OR
t EN tMDV tA Previous Data tEN t MDV tA W1[17] W2 [17] W1[17] tA W3 [17] tA No Operation W2 [17] tDIS tDIS
B0-35 (FWFT Mode)
Notes: 15. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH. 16. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X). 17. Read From FIFO.
11
PRELIMINARY
Switching Waveforms (continued)
CY7C43643AV CY7C43663AV/CY7C43683AV
Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes) CLKB
[18]
EF/OR CSB W/RB MBB
HIGH
tENS tENH
ENB B0-8 (Standard Mode)
OR
tEN tMDV tA Previous Data tEN tMDV tA Read 1 tA Read 1 tA Read 2 Read 3 tA Read 2 tA tA Read 3 tA Read 4 No OperationtDIS Read 4 tDIS Read 5
B0-8 (FWFT Mode)
Port B Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes) [19] CLKB EF/OR CSB W/RB MBB
tENS tENH
ENB B0-17 (Standard Mode)
OR
tEN tMDV tA Previous Data t EN tMDV tA Read 1 Read 2 Read 1 tA Read 3 tA No Operation Read 2 tDIS tDIS
B0-17 (FWFT Mode)
Notes: 18. Unused bytes B9-17, B18-26 , and B27-35 contain all zeroes for byte-size reads. 19. Unused bytes B18-35 contains all zeroes for word-size reads.
12
PRELIMINARY
Switching Waveforms (continued)
CY7C43643AV CY7C43663AV/CY7C43683AV
OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
tCLK tCLKH tCLKL
[20]
CLKA
CSA W/RA MBA
LOW HIGH tENS tEN
t ENS tEN
ENA FF/IR A0-35 CLKB
HIGH t DS tDH W1 tSKEW1[21] tCLKH tCLKL
tCLK
tREF
tREF
EF/OR CSB W/RB
FIFO Empty
LOW
HIGH
MBB ENB
LOW tENS tENH
tA
B0-35
Old Data in FIFO Output Register
W1
Notes: 20. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively. 21. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load of the first word to the output register may occur one CLKB cycle later than shown.
13
PRELIMINARY
Switching Waveforms (continued)
CY7C43643AV CY7C43663AV/CY7C43683AV
EF Flag Timing and First Data Read Fall Through when FIFO is Empty (CY Standard Mode)
tCLK tCLKH t CLKL
[20]
CLKA
CSA W/RA MBA
LOW HIGH tENS tENH
tENS tENH
ENA FF/IR A0-35 CLKB
tCLK tREF tREF
HIGH tDS tDH W1 tSKEW[22] tCLKH tCLKL
EF/OR CSB W/RB MBB ENB
FIFO Empty
LOW
HIGH
LOW t ENS tENH
tA
B0-35
W1
Notes: 22. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
14
PRELIMINARY
Switching Waveforms (continued)
CY7C43643AV CY7C43663AV/CY7C43683AV
IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode) [23]
tCLK tCLKH tCLKL
CLKB
CSB W/RB MBB
LOW
HIGH
tENS tENH
ENB EF/OR B0-35 CLKA
tCLK tWFF tWFF HIGH tA
Previous Word in FIFO Output Register Next Word From FIFO
tSKEW1
[24]
tCLKH
tCLKL
FF/IR CSA W/RA MBA
FIFO Full
LOW
HIGH t ENS tENH
tENS tENH
ENA
tDS tDH
A0-35
To FIFO
Notes: 23. If Port B size is word or byte, t SKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long-word, respectively. 24. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
15
PRELIMINARY
Switching Waveforms (continued)
CY7C43643AV CY7C43663AV/CY7C43683AV
FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode)
tCLK tCLKH tCLKL
[23]
CLKB
CSB W/RB MBB
LOW
HIGH
tENS tENH
ENB EF/OR B0-35 CLKA
tCLK tWFF t WFF HIGH tA
Previous Word in FIFO Output Register Next Word From FIFO
tSKEW1[25]
tCLKH
tCLKL
FF/IR CSA W/RA MBA
FIFO Full
LOW
HIGH tENS tENH
t ENS tENH
ENA
tDS tDH
A0-35
Note: 25. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
16
PRELIMINARY
Switching Waveforms (continued)
CY7C43643AV CY7C43663AV/CY7C43683AV
Timing for AF when FIFO is Almost Full (CY Standard and FWFT Modes)
tSKEW2[29]
[26, 27, 28]
CLKA
tENS tENH
ENA
tPAF
AF
t PAF (D-Y1)Words in FIFO
[D-(Y1+1)] Words in FIFO
CLKB
tENS
tENH
ENB
Timing for AE when FIFO is Almost Empty (CY Standard and FWFT Modes) CLKA
tENS tENH
[30, 31]
ENA
tSKEW2[32]
CLKB
tPAE tPAE (X1+1)Words in FIFO t ENS tENH
AE ENB
X1 Word in FIFO
Notes: 26. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO. 27. D = Maximum FIFO Depth = 1K for the CY7C43643, 4K for the 43663, and 16K for the CY7C43683. 28. If Port B size is word or byte, t SKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. 29. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown. 30. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO. 31. If Port B size is word or byte, AE is set LOW by the last word or byte read from FIFO, respectively. 32. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
17
PRELIMINARY
Switching Waveforms (continued)
CY7C43643AV CY7C43663AV/CY7C43683AV
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes) CLKA
t ENS tENH
[33]
CSA
tENS t ENH
W/RA
tENS tENH
MBA
tENS t ENH
ENA
tDS tDH W1
A0-35 CLKB
tPMF
tPMF
MBF1 CSB W/RB MBB
tENS tENH
ENB
t EN tMDV FIFO Output Register tPMR tDIS W1 (Remains valid in Mail1 Register after read)
B0-35
Note: 33. If Port B is configured for word size, data can be written to the Mail1 register using A0-17 (A18-35 are don't care inputs). In this first case B0-17 will have valid data (B18-35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-8 (A9-35 are don't care inputs). In this second case, B0-8 will have valid data (B9-35 will be indeterminate).
18
PRELIMINARY
Switching Waveforms (continued)
CY7C43643AV CY7C43663AV/CY7C43683AV
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes) CLKB
tENS tENH
[34]
CSB
tENS tENH
W/RB
t ENS tENH
MBB
tENS tENH
ENB
tDS t DH
B0-35 CLKA
W1
tPMF
tPMF
MBF2 CSA W/RA MBA
tENS tENH
ENA
tEN tMDV FIFO2 Output Register tPMR tDIS W1 (Remains valid in Mail2 Register after read)
A0-35
FIFO Retransmit Timing RT1
[34, 35, 36, 37]
t PRT
t RTR
ENB EFB/FFA
Notes: 34. If Port B is configured for word size, data can be written to the Mail2 register using B0-17 (B18-35 are don't care inputs). In this first case A0-17 will have valid data (A18-35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-8 (B9-35 are "don't care" inputs). In this second case, A0-8 will have valid data (A9-35 will be indeterminate). 35. Clocks are free-running in this case. 36. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 37. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
19
PRELIMINARY
Signal Description
Master Reset (MRS1, MRS2) The FIFO memory of the CY7C436X3AV undergoes a complete reset by taking its associated Master Reset (MRS1, MRS2) input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset input can switch asynchronously to the clocks. A Master Reset initializes the internal read and write pointers and forces the Full/Input Ready flag (FF/IR) LOW, the Empty/ Output Ready flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the Almost Full flag (AF) HIGH. A Master Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the FIFO's Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. A Master Reset must be performed on the FIFO after power up, before data is written to its memory. A LOW-to-HIGH transition on a FIFO Master Reset (MRS1, MRS2) input latches the value of the Big Endian (BE) input, determining the order by which bytes are transferred through Port B. A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2) input latches the values of the Flag Select (FS0, FS1) and Serial Programming Mode (SPM) inputs for choosing the Almost Full and Almost Empty offset programming method (see Almost Empty and Almost Full flag offset programming below). Partial Reset (PRS) Each of the two FIFO memories of the CY7C436X3AV undergoes a limited reset by taking its associated Partial Reset (PRS) input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset inputs can switch asynchronously to the clocks. A Partial Reset initializes the internal read and write pointers and forces the Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the Almost Full flag (AF) HIGH. A Partial Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Partial Reset, the FIFO's Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. Whatever flag offsets, programming method (parallel or serial), and timing mode (FWFT or CY Standard mode) are currently selected at the time a Partial Reset is initiated, those settings will remain unchanged upon completion of the reset operation. A Partial Reset may be useful in the case where reprogramming a FIFO following a Master Reset would be inconvenient. Big Endian/First-Word Fall-Through (BE/FWFT) This is a dual-purpose pin. At the time of Master Reset, the BE select function is active, permitting a choice of Big or Little Endian byte arrangement for data written to or read from Port B. This selection determines the order by which bytes (or words) of data are transferred through this port. For the following illustrations, assume that a byte (or word) bus size has been selected for Port B. (Note that when Port B is configured for a long-word size, the Big Endian function has no application and the BE input is a "don't care.") A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs go from LOW to HIGH will select a Big Endian arrangement. When data is moving in the direction from Port A to Port B, the most significant byte (word) of the long-word
CY7C43643AV CY7C43663AV/CY7C43683AV
written to Port A will be read from Port B first; the least significant byte (word) of the long-word written to Port A will be read from Port B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be read from Port A as the most significant byte (word) of the longword; the byte (word) written to Port B last will be read from Port A as the least significant byte (word) of the long-word. A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs go from LOW to HIGH will select a Little Endian arrangement. When data is moving in the direction from Port A to Port B, the least significant byte (word) of the long-word written to Port A will be read from Port B first; the most significant byte (word) of the long-word written to Port A will be read from Port B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be read from port A as the least significant byte (word) of the longword; the byte (word) written to Port B last will be read from Port A as the most significant byte (word) of the long-word. After Master Reset, the FWFT select function is active, permitting a choice between two possible timing modes: CY Standard Mode or First-Word Fall-Through (FWFT) Mode. Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the BE/FWFT input at the second LOW-to-HIGH transition of CLKA will select CY Standard Mode. This mode uses the Empty Flag function (EF) to indicate whether or not there are any words present in the FIFO memory. It uses the Full Flag function (FF) to indicate whether or not the FIFO memory has any free space for writing. In CY Standard Mode, every word read from the FIFO, including the first, must be requested using a formal read operation. Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/FWFT input during the next LOW-to-HIGH transition of CLKA will select FWFT Mode. This mode uses the Output Ready function (OR) to indicate whether or not there is valid data at the data outputs (B0-35). It also uses the Input Ready function (IR) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a formal read operation. Following Master Reset, the level applied to the BE/FWFT input to choose the desired timing mode must remain static throughout the FIFO operation. Programming the Almost Empty and Almost Full Flags Two registers in the CY7C436X3AV are used to hold the offset values for the Almost Empty and Almost Full flags. The Port A Almost Empty flag (AE) offset register is labeled X. The Port B Almost Full flag (AF) offset register is labeled Y. The index of each register name corresponds with preset values during the reset of a FIFO, programmed in parallel using the FIFO's Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 1). To load a FIFO's Almost Empty flag and Almost Full flag offset registers with one of the three preset values listed in Table 1, the Serial Program Mode (SPM) and at least one of the flagselect inputs must be HIGH during the LOW-to-HIGH transition of its Master Reset input (MRS1, MRS2). For example, to load the preset value of 64 into X and Y, SPM, FS0 and FS1 must be HIGH when the FIFO reset (MRS1, MRS2) returns HIGH. When using one of the preset values for the flag offsets, the FIFO can be reset simultaneously or at different times.
20
PRELIMINARY
To program the X and Y registers from Port A, perform a Master Reset on both FIFOs simultaneously with SPM HIGH and FS0 and FS1 LOW during the LOW-to-HIGH transition of MRS1, MRS2. After this reset is complete, the first two writes to the FIFO do not store data in RAM but load the offset registers in the order Y and X. The Port A data inputs used by the offset registers are (A0-9), (A 0-11), or (A 0-13), for the CY7C436X3AV, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 1012 for the CY7C43643AV; 1 to 4092 for the CY7C43663AV; 1 to 16380 for the CY7C43683AV. Before programming the offset registers, FF/IR is set HIGH. FIFOs begin normal operation after programming is complete. To program the X and Y registers serially, initiate a Master Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH during the LOW-to-HIGH transition of MRS1, MRS2. After this reset is complete, the X and Y register values are loaded bitwise through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/SEN input is LOW. Twenty, twentyfour, or twenty-eight bit writes are needed to complete the programming for the CY7C436X3AV, respectively. The two registers are written in the order Y then finally X. The first-bit write stores the most significant bit of the Y register and the last-bit write stores the least significant bit of the X register. Each register value can be programmed from 1 to 1020 (CY7C43643AV), 1 to 4092 (CY7C43663AV), or 1 to 16380 (CY7C43683AV). When the option to program the offset registers serially is chosen, the Port A Full/Input Ready (FF/IR) flag remains LOW until all register bits are written. FF/IR is set HIGH by the LOWto-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO operation. SPM, FS0/SD, and FS1/SEN function the same way in both CY Standard and FWFT modes. FIFO Write/Read Operation The state of the Port A data (A0-35) lines is controlled by Port A Chip Select (CSA) and Port A Write/Read Select (W/RA). The A0-35 lines are in the high-impedance state when either CSA or W/RA is HIGH. The A0-35 lines are active outputs when both CSA and W/RA are LOW. Data is loaded into the FIFO from the A0-35 inputs on a LOWto-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH. (see Table 2). FIFO writes on Port A are independent of any concurrent Port B operation. The Port B control signals are identical to those of Port A with the exception that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read select (W/RA). The state of the Port B data (B0-35) lines is controlled by the Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-35 lines are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-35 lines are active outputs when CSB is LOW and W/RB is HIGH. Data is read from the FIFO to the B 0-35 outputs by a LOW-toHIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and EF/OR is HIGH (see Table 3). FIFO reads and writes on Port B are independent of any concurrent Port A operation.
CY7C43643AV CY7C43663AV/CY7C43683AV
The set-up and hold time constraints to the port clocks for the port Chip Selects and Write/Read Selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port's Chip Select and Write/Read Select may change states during the set-up and hold time window of the cycle. When operating the FIFO in FWFT Mode with the Output Ready flag LOW, the next word written is automatically sent to the FIFO's output register by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port's Chip Select, Write/Read Select, Enable, and Mailbox Select. When operating the FIFO in CY Standard Mode, regardless of whether the Empty Flag is LOW or HIGH, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port's Chip Select, Write/ Read Select, Enable, and Mailbox Select. Synchronized FIFO Flags Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of the metastable events when CLKA and CLKB operate asynchronously to one another. EF/ OR and AE are synchronized to CLKA. FF/IR and AF are synchronized to CLKB. Table 4 shows the relationship of each port flag to the FIFO. Empty/Output Ready Flags (EF/OR) These are dual-purpose flags. In the FWFT Mode, the Output Ready (OR) function is selected. When the Output Ready flag is HIGH, new data is present in the FIFO output register. When the Output Ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. In the CY Standard Mode, the Empty Flag (EF) function is selected. When the Empty Flag is HIGH, data is available in the FIFO's RAM memory for reading to the output register. When Empty Flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. The Empty/Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. For both the FWFT and CY Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. In FWFT Mode, from the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three cycles have not elapsed since the time the word was written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register. In the CY Standard Mode, from the time a word is written to a FIFO, the Empty flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty flag
21
PRELIMINARY
synchronizing clock. Therefore, an Empty flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles have not elapsed since the time the word was written. The Empty flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing the Empty flag HIGH; only then can data be read. A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle. Full/Input Ready Flags (FF/IR) This is a dual-purpose flag. In FWFT Mode, the Input Ready (IR) function is selected. In CY Standard Mode, the Full Flag (FF) function is selected. For both timing modes, when the Full/Input Ready flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored. The Full/Input Ready flag of a FIFO is synchronized to the port clock that writes data to its array. For both FWFT and CY Standard modes, each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls a Full/ Input Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, a Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the read sets the Full/ Input Ready flag HIGH. A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle. Almost Empty Flags (AE) The Almost Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost Empty flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The Almost Empty state is defined by the contents of register X for AE. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost Empty flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing (X+1) or more words remains LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost Empty flag is set HIGH by the second LOW-to-HIGH
CY7C43643AV CY7C43663AV/CY7C43683AV
transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. Almost Full Flags (AF) The Almost Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost Full flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The Almost Full state is defined by the contents of register Y for AF. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (1024-Y), (4096-Y), or (16384-Y), for the CY7C436X3AV respectively. An Almost Full flag is HIGH when the number of words in its FIFO is less than or equal to [1024-(Y+1)], [4096-(Y+1)], or [16384-(Y+1)], for the CY7C436X3AV respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost Full flag synchronizing clock are required after a FIFO read for its Almost Full flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing [1024/4096/16384-(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [1024/4096/16384-(Y+1)]. An Almost Full flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [1024/4096/16384-(Y+1)]. A LOWto-HIGH transition of an Almost Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [1024/4096/16384-(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. Mailbox Registers Each FIFO has a 36-bit bypass register to pass command and control information between Port A and Port B without putting it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. The usable width of both the Mail1 and Mail2 registers matches the selected bus size for Port B. A LOW-to-HIGH transition on CLKA writes A0-35 data to the Mail1 Register when a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the selected Port A bus size is also 36 bits, then the usable width of the Mail1 Register employs data lines A0-35. If the selected Port A bus size is 18 bits, then the usable width of the Mail1 Register employs data lines A0-17. (In this case, A18-35 are don't care inputs.) If the selected Port A bus size is 9 bits, then the usable width of the Mail1 Register employs data lines A 0-8. (In this case, A9-35 are "Don't Care" inputs.) A LOW-to-HIGH transition on CLKB writes B0-35 data to the Mail2 Register when a Port B write is selected by CSB, W/RB, and ENB with MBB HIGH. If the selected Port B bus size is also 36 bits, then the usable width of the Mail2 Register em-
22
PRELIMINARY
ploys data lines B 0-35. If the selected Port B bus size is 18 bits, then the usable width of the Mail2 Register employs data lines B0-17. (In this case, B18-35 are don't care inputs.) If the selected Port B bus size is 9 bits, then the usable width of the Mail2 Register employs data lines B0-8. (In this case, B9-35 are don't care inputs.) Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port Mailbox Select input is LOW and from the mail register when the port Mailbox Select input is HIGH. The Mail1 Register flag (MBF1) is set HIGH by a LOW-toHIGH transition on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B 0-35. For an 18-bit bus size, 18 bits of mailbox data are placed on B0-17. (In this case, B18-35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are placed on B0-8. (In this case, B9-35 are indeterminate.) The Mail2 Register flag (MBF2) is set HIGH by a LOW-toHIGH transition on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on A0-35. For an 18-bit bus size, 18 bits of mailbox data are placed on A0-17. (In this case, A18-35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are placed on A0-8. (In this case, A9-35 are indeterminate.) The data in a mail register remains intact after it is read and changes only when new data is written to the register. The Endian Select feature has no effect on the mailbox data. Bus Sizing The Port B bus can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data read from FIFO. The levels applied to the Port B Bus Size Select (SIZE) and the Bus Match Select (BM) determine the Port B bus size. These levels should be static throughout FIFO operation. Both bus size selections are implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH. Two different methods for sequencing data transfer are available for Port B when the bus size selection is either byte-or word-size. They are referred to as Big Endian (most significant byte first) and Little Endian (least significant byte first). The level applied to the Big Endian Select (BE) input during the LOW-to-HIGH transition of MRS1/MRS2 selects the endian
CY7C43643AV CY7C43663AV/CY7C43683AV
method that will be active during FIFO operation. BE is a don't care input when the bus size selected for Port B is long-word. The endian method is implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH. Only 36-bit long-word data is written to or read from the two FIFO memories on the CY7C436X3AV. Bus-matching operations are done after data is read from the FIFO. These busmatching operations are not available when transferring data via mailbox registers. Furthermore, both the word- and bytesize bus selections limit the width of the data bus that can be used for mail register operations. In this case, only those byte lanes belonging to the selected word- or byte-size bus can carry mailbox data. The remaining data outputs will be indeterminate. The remaining data inputs will be don't care inputs. For example, when a word-size bus is selected, then mailbox data can be transmitted only between A0-17 and B0-17. When a byte-size bus is selected, then mailbox data can be transmitted only between A 0-8 and B0-8. Bus-Matching FIFO Reads Data is read from the FIFO RAM in 36-bit long-word increments. If a long-word bus size is implemented, the entire longword immediately shifts to the FIFO output register. If byte or word size is implemented on Port B, only the first one or two bytes appear on the selected portion of the FIFO output register, with the rest of the long-word stored in auxiliary registers. In this case, subsequent FIFO reads output the rest of the long-word to the FIFO output register. When reading data from the FIFO in the byte or word format, the unused B0-35 outputs are indeterminate. Retransmit (RT) The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last reset cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. CLKA and CLKB may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted.
23
PRELIMINARY
CY7C43643AV CY7C43663AV/CY7C43683AV
A27-35
A18-26
BYTE ORDER ON PORT A:
BE X BM L SIZE X
A9-17
A0-8
A
B27-35
B
B18-26
C
B9-17
D
B0-8
Write to FIFO
A
B27-35
B
B18-26
C
B9-17
D
B0-8
Read from FIFO
(a) LONG WORD SIZE 1st: Read from FIFO 2nd: Read from FIFO
BE H
BM H
SIZE L B27-35 B18-26
A
B9-17
B
B0-8
C
B27-35 BE L BM H SIZE L B27-35 B18-26 B18-26 B9-17
D
B0-8
(b) WORD SIZE - BIG ENDIAN 1st: Read from FIFO 2nd: Read from FIFO
C
B9-17
D
B0-8
A
B27-35 BE H BM H SIZE H B27-35 B18-26 B9-17 B9-17
B
B0-8
(c) WORD SIZE - LITTLE ENDIAN
B18-26
A
B0-8
1st: Read from FIFO 2nd: Read from FIFO 3rd: Read from FIFO 4th: Read from FIFO
B
B27-35 B18-26 B9-17 B0-8
C
B27-35 B18-26 B9-17 B0-8
D
(d) BYTE SIZE - BIG ENDIAN
B27-35 BE L BM H SIZE H B27-35 B18-26 B9-17 B18-26 B9-17 B0-8
D
B0-8
1st: Read from FIFO 2nd: Read from FIFO 3rd: Read from FIFO 4th: Read from FIFO
C
B27-35 B18-26 B9-17 B0-8
B
B27-35 B18-26 B9-17 B0-8
A
(e) BYTE SIZE - LITTLE ENDIAN
24
PRELIMINARY
..able
CY7C43643AV CY7C43663AV/CY7C43683AV
Table 1. Flag Programming SPM H H H H L L L L FS1/SEN H H L L H H L L FS0/SD H L H L L H H L MRS1/MRS2 X and Y Registers[38] 64 16 8 Parallel programming via Port A Serial programming via SD Reserved Reserved Reserved
Table 2. Port A Enable Function CSA H L L L L L L L W/RA X H H H L L L L ENA X L H H L H L H MBA X X L H L L H H CLKA X X X X A0-35 Outputs In high-impedance state In high-impedance state In high-impedance state In high-impedance state Active, Mail2 register Active, Mail2 register Active, Mail2 register Active, Mail2 register Port Function None None FIFO write Mail1 write None None None Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function CSB H L L L L L L L W/RB X L L L H H H H ENB X L H H L H L H MBB X X L H L L H H CLKB X X X X B0-35 Outputs In high-impedance state In high-impedance state In high-impedance state In high-impedance state Active, FIFO output register Active, FIFO output register Active, Mail1 register Active, Mail1 register Port Function None None None Mail2 write None FIFO read None Mail1 read (set MBF1 HIGH)
Note: 38. X register holds the offset for AE; Y register holds the offset for AF.
25
PRELIMINARY
Table 4. FIFO Flag Operation (CY Standard and FWFT Modes) Number of Words in FIFO Memory[39, 40, 41, 42] CY7C43643AV 0 1 TO X1 (X1+1) to [1024-(Y1+1)] CY7C43663AV 0 1 TO X1 (X1+1) to [4096-(Y1+1)] CY7C43683AV 0 1 TO X1 (X1+1) to [16384-(Y1+1)] (16384-Y1) to 16383 16384
CY7C43643AV CY7C43663AV/CY7C43683AV
Synchronized to CLKA EF/OR L H H H H AE L L H H H
Synchronized to CLKB AF H H H L L FF/IR H H H H L
(1024-Y1) to 1023 (4096-Y1) to 4095 1024 4096
Table 5. Data Size for FIFO Long-Word Reads Size Mode[43] BM L SIZE X BE X A27-35 A Data Written to FIFO2 A18-26 B A9-17 C A0-8 D B27-35 A Data Read From FIFO2 B18-26 B B9-17 C B0-8 D
Table 6. Data Size for Word Reads Size Mode[43] BM H H SIZE L L BE H L A27-35 A A Data Written to FIFO A18-26 B B A9-17 C C A0-8 D D 1 2 1 2 Table 7. Data Size for Byte Reads from FIFO Size Mode[43] BM H SIZE H BE H A27-35 A Data Written to FIFO A18-26 B A9-17 C A0-8 D 1 2 3 4 H H L A B C D 1 2 3 4 Read No. Data Read From FIFO B0-8 A B C D D C B A Read No. Data Read From FIFO B9-17 A C C A B0-8 B D D B
Notes: 39. X1 is the Almost Empty offset for FIFO used by AE. Y1 is the Almost Full offset for FIFO used by AF. Both X1 and Y1 are selected during a FIFO reset or Port A programming. 40. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 41. Data in the output register does not count as a "word in FIFO memory". Since in FWFT Mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 42. The OR and IR functions are active during FWFT mode; the EF and FFA functions are active in CY Standard Mode. 43. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
26
PRELIMINARY
CY7C43643AV CY7C43663AV/CY7C43683AV
3.3V 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching
Speed (ns) 7 10 15 Ordering Code CY7C43643AV-7AC CY7C43643AV-10AC CY7C43643AV-15AC Package Name A128 A128 A128 Package Type 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package Operating Range Commercial Commercial Commercial
3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching
Speed (ns) 7 10 15 Ordering Code CY7C43663AV-7AC CY7C43663AV-10AC CY7C43663AV-15AC Package Name A128 A128 A128 Package Type 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package Operating Range Commercial Commercial Commercial
3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching
Speed (ns) 7 10 15 15 Ordering Code CY7C43683AV-7AC CY7C43683AV-10AC CY7C43683AV-15AC CY7C43683AV-15AI Package Name A128 A128 A128 A128 Package Type 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package Operating Range Commercial Commercial Commercial Industrial
Shaded area contains advance information.
Document #: 38-00776
27
PRELIMINARY
Package Diagram
CY7C43643AV CY7C43663AV/CY7C43683AV
128-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

▲Up To Search▲

Price & Availability of CY7C43683AV

	To Download CY7C43683AV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .